TEJ KORAT
Apex
Summary
With more than a decade of experience in RTL2GDSII, I have successfully completed over 15 tapeouts. My leadership skills have been honed over two years of managing SoC Physical Design teams. I am a proactive professional with a deep understanding of Physical Design Implementation, Methodology, Strategy, program management, people management, and SOC Execution. My expertise lies in various SoCs/ASICs, which are vital for products that prioritize Performance, Power, Area, Cost, and Time to Market. Additionally, I am currently pursuing an executive MBA at UNC.
Overview
12
12
years of professional experience
Work History
Principal Hardware Engineering Manager
Microsoft Corp
09.2020 - Current
- As a leader, I guide a team of physical designers in implementing high-speed IPs for N3E compute/AI chips
- I hold responsibility for IP-Top and various subsystems, encompassing partitioning, floor planning, place and route, and timing / PV / PI closure
- In my role as the physical design lead (RTL2GDS), I formulated the PPA recipe for Microsoft IPs and integrated it into multiple Subchips, including other high-speed interface IPs
- I supervised the development of several high-performance blocks, such as L3 cache, D2D, and DDR MC
- I ensured a swift response to floorplan modifications and provided physical design feedback to the RTL designer on uArch feasibility for 5nm/3nm technology
- My experience extends to hierarchical design planning to minimize area and place and route for timing and congestion-critical designs with extended runtimes
- I have managed and deployed libraries (80+ IPs) and specialize in tool and process migrations
- I collaborate with methodology teams and vendors to develop improved workflows
- I manage SOC Programs using Azure DevOps.
Sr Staff IC Design Engineer
Broadcom Inc
06.2012 - 09.2020
- Successfully completed tapped out 15+ SOC‘s with different challenges and learning opportunity of tool knowledge, low power understanding, IP know how, customer architecture and design
- Single handedly executed implementation from netlist to GDSII of full SOC including 6 hierarchical blocks in TSMC 7nm
- Worked with tool vendors to develop the flow modifications and tool updates to handle 7nm technology physical rules
- Responsible for all aspects of physical design for fullchip/blocks covering floor-planning, budgeting, clock tree planning & analysis, placement, scan reordering, clock tree synthesis, placement optimization's, routing, timing and SI analysis/closure, ECO tasks (both timing and functional), EMIR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation
- Extensive knowledge of backend design closure flow for custom SoC (System on Chip)
- Worked on numerous full chip & block level Netlist to GDS projects
- Knowledge integration /implementation of low power IPs Serdes, NVME/AHCI, DDR, NAND & CPU
- Comprehensive knowledge of PrimeTime (static timing analysis) including Eco flow
- Working knowledge of Extraction & STA methodology and tools
- Improved productivity by developing methodologies, flow automation and existing flows.
Education
Executive MBA -
University of North Carolina
Chapel Hill, NC06.2024
B.E. Electronics and Communication -
University of Pune
01.2011
Skills
- Fast Learner
- Leadership Skills
- Physical design
- People & Program management
- Python
- TCL
- EDA tools
- Workforce Management
- Performance Management
- Expense Tracking
- Staff Development
Timeline
Principal Hardware Engineering Manager
Microsoft Corp
09.2020 - Current
Sr Staff IC Design Engineer
Broadcom Inc
06.2012 - 09.2020
Executive MBA -
University of North Carolina
B.E. Electronics and Communication -
University of Pune
Similar Profiles
Sudaivi Vidyut JadhavSudaivi Vidyut Jadhav
Cyber Security Researcher at Microsoft CorpCyber Security Researcher at Microsoft Corp
Dominique KellyDominique Kelly
Digital Cloud Acquisition at Microsoft CorpDigital Cloud Acquisition at Microsoft Corp
Robert B BainRobert B Bain
Fixed Asset Accountant at Microsoft CorpFixed Asset Accountant at Microsoft Corp